Conserving power consumption in computer systems is a well-known objective in the computer arts. In addition to prolonging battery life in portable computers, reducing power consumption in a computer system may result in real energy savings, particularly when multiplied by the large number of installed Personal Computers (PCs) in the world. The ENERGY STAR standard promulgated by the U.S. government requires that computers meeting this standard use no more than 60 Watts when idle.
Various control system are known for generating video displays on portable computers, PCs and other computing systems, including VGA and SVGA controllers, so-called graphics accelerators (e.g., 2D and 3D), flat panel display controllers, and the like. Such controllers may be referred to as "video controllers", however, with the advent of full motion video in computer systems, such a term may be a misnomer. For the purposes of this application, such a control system may be referred to a "display controller".
FIG. 1 shows an example of a prior art display controller which is presented here for purposes of illustration only. Such a prior art display controller is disclosed, for example, in Bril et al., U.S. Pat. No. 5,539,428, issued Jul. 23, 1996 and incorporated herein by reference. The present invention may also be applied to other types of display controllers without departing from the spirit or scope of the invention.
Referring to FIG. 1 there is shown an internal block diagram of a display controller 101. System data may be written to display controller 101 via system data bus 105, system control bus 106, and system address bus 108 (hereinafter generally referred to as system busses 105, 106, 108) may pass through CPU interface 120 to control other elements of display controller 101 via an internal data and control bus 125. Status and other data may also be read from the other elements in display controller 101 via internal data and control bus 125, CPU interface 120 and system busses 105, 106, 108.
Data written to display controller 101, intended to be stored in an external video memory (not shown), may be written through and modified as necessary by graphics controller 117, then written to memory controller 116. Memory controller 116 drives appropriate values on video memory control bus 109 and video memory address bus 110, and drives data out on video memory data bus 111.
Memory controller 116 may also be responsible for reading memory data needed to define video data. Memory controller 116 may drive appropriate values on video memory control bus 109 and video memory address bus 110, and receives video memory data on video memory data bus 111. Video data is stored in an external video memory (not shown) coupled to video memory busses 109, 110 and 111.
In operation, video data from memory controller 116 passes through video FIFO 118, then is modified as necessary in attribute controller 121 before being output on video output data bus 104. Data on video output data bus is further modified by video output block 123, and driven out on video output 103. Video output block 123 may comprise, for example, a RAMDAC (Random Access Memory Digital to Analog Converter). Video signals entering the RAMDAC may comprise, for example, data which describe a color to be displayed.
Such data may define a number representative of a particular color, but not necessarily the color itself. The RAM portion of the RAMDAC contains a lookup table which converts this number into a digital signal representing a color value. The contents of the lookup table can be altered by software such that a particular color value can be assigned to a different number (or vice versa). The DAC portion of the RAMDAC converts this color value to an analog output, for example, analog VGA or the like, which is then transmitted on video output 103.
CRT controller 119 may generate signals for video output control bus 102. Memory controller 116,may use one of internal clocks 126. CRT controller 119, video FIFO 118, attribute controller 121, and video output 123 may use a different, asynchronous one of internal clocks 126. Techniques known in the art are used to synchronize the transfer of data from memory controller 116 to video FIFO 118. In normal operation, internal clocks 126 are generated by clock synthesizer 122, which may use system reference clock 107.
In the prior art, memory used with display controller 101 typically comprised conventional dynamic random access memory (DRAM). Such memories were relatively inexpensive and suitable for use with low resolution displays of relative static images (e.g., word processing, spreadsheets, simple CAD systems, and the like). However, with the advent of higher resolution displays with higher refresh rates, as well as the use of full motion video, 2-D and 3-D graphics, faster memories and display controller clock speeds have been employed. Memories with faster access techniques and interfaces have been employed (e.g., EDO DRAM, RDRAM, VRAM, and the like).
However, such memory devices may require higher power consumption due to the use of advanced MOS technology. Unlike conventional DRAMS, such memories may use the same amount of power regardless of whether they are being accessed. In the prior art, it is known to stop clock signals to memory devices during power reduction modes (e.g., a "sleep" or "suspend" mode, where clock signals to substantially an entire computer system are shut down or severely slowed). However, such a display memory may remain inactive between screen refreshes and CPU access for a significant amount of time, and thus consume power even when not in use.